According to the question, one instruction takes 5 cycles on average, and the CPU is occupied 95 % of the time executing those instructions. Three of the five cycles are required for memory operations. DMA is unable to access the memory at this period.

So there are only two cycles for DMA to use for 95% of the time. For 95% time DMA uses:-

= 0.95∗2 cycles

For rest of the 5% time, CPU will not be executing any instruction, so all cycles are available for DMA to perform operations, so DMA uses:-

= 0.05∗5 cycles

Total number of cycles available for DMA are:-

= (0.05∗5+0.95∗2) cycles

CPU can execute 106 instructions in one second . So transfer rate for DMA is:-

= 106∗(0.05∗5+0.95∗2)

= 2.15∗106

= 227.9